With reference to FIGS. 1 and 3A, a conventional method for programming and erasing a conventional flash memory cell is described.
FIG. 1 is a schematic circuit diagram of a NOR type flash memory cell array and a table of conventional bias voltage conditions for some modes of operations, and FIG. 3A is a schematic cross-sectional diagram which shows the conventional mechanisms of programming and erasing.
In order to program a flash memory cell, a voltage of about 9V is applied to a control gate 10 of the selected memory cell, a power supply voltage Vcc of, e.g., 5V is applied to a bit line(drain) 40 of the selected memory cell and a ground voltage of, e.g., 0V is applied to other bit lines(not shown) of unselected memory cells(not shown). Under this bias condition, hot electrons are generated in the channel(not shown) in the vicinity of the drain of the selected memory cell and injected into a floating gate 20 of the memory cell.
While the above described programming process, a large amount of current of 300 .mu.A to 500 .mu.A is dissipated per each memory cell. Therefore, under the above described bias condition, only one word or byte of memory cells can be programmed at the same time. This becomes especially serious problem for portable apparatus which uses battery as power supply.
Further, in order to erase the flash memory cell, a voltage of about -9V is applied to the control gate 10 of the selected memory cell, the power supply voltage Vcc of 5V is applied to the source 30 of the selected memory cell. While erasing the flash memory cell, the drain 40 is left floated, which means the drain is not coupled to anything. Then, a strong electric field is established between the floating gate 20 and the source 30, so that the electrons stored in the floating gate 20 are ejected to the source 30 by Fowler-Nordheim tunneling("F-N tunneling"). Due to these ejected electrons, a leakage current is generated in the vicinity of the source 30.
One of the solutions to reduce this leakage current is to form a double diffused junction as the source junction. However, the double diffused source junction results in a lateral diffusion, so that the size of the memory cell is increased.